RETRIEVAL · RECEIPT · MEASURED 2026-10-02
USPTO patents
Granted US patents, full text including claims.
4,008 documents · 378,252 passages · 200 questions scored
BEFORE AND AFTER · SAME QUESTIONS AT EVERY STEP
WHAT MOVED THE NUMBER.
01 · NDCG@10 0.670
Cross-encoder reranker
A cross-encoder rereads the top candidates against the question and reorders them.
02 · NDCG@10 0.801
Document identity in every passage, and routing
Each passage carries a one-line identity of the patent it came from, and a question that names a patent searches it first.
METHOD · AND ITS LIMIT
HOW IT IS MEASURED.
200 questions per corpus, each naming its subject, one labelled passage per question, scored on the product's retrieval receipt; nDCG@10 with a bootstrap 95% interval; questions are model-written and so easier than human test sets: use these to compare configurations, not as an absolute claim.
20 OF 200 QUESTIONS · PICKED BY HASH, NOT BY HAND
THE QUESTIONS, WITH THEIR RESULTS.
A fixed sample across the results: passages ranked first, passages found lower in the ten, and misses.
In this patent application for etching dielectric material using WF6, why are certain well-known process operations omitted from the detailed description?
Labelled document: US10847377B2 patent — semiconductor etching method using WF6 chemistry for DRAM fabrication — 2020
In the above description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been…
According to this patent for a method of measuring electromigration, how is the extent of degradation in a microelectronic package interconnect calculated using voltage drop values?
Labelled document: Method for measuring electromigration in microelectronic interconnects — US Patent — 2002
Disadvantageously, long test cycles are required to measure the mean time to failure (MTTF) even using accelerated values for the current densities and temperatures. In contrast to methods that determine the activation energy from the mean time to failure, the embodiments of the present invention…
What is the purpose of the interconnect layers in the microelectronic assemblies fabricated using hybrid manufacturing?
Labelled document: Microelectronic assemblies using hybrid manufacturing for photonic and electronic integration — US patent application — 2025
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1640 ) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in FIG. 14 as interconnect layers 1606 1610 ). For…
Why is the analog-to-digital conversion circuitry positioned outside of the sensor array area in this FET array sequencing system patent?
Labelled document: FET arrays for nucleic acid sequencing — US patent — 2023
As will be understood by those of skill in the art, the ability to miniaturize sequencing reactions reduces the time, cost and labor involved in sequencing of large genomes (such as the human genome). Of course, it should be appreciated that pixel sizes greater than 10 micrometers (e.g., on the…
What alternative materials can be used to construct nanowire devices that utilize the gate structure described in the vertical super-thin body (VSTB) semiconductor device patent?
Labelled document: Semiconductor device with vertical super-thin body — US patent application — 2012
Embodiments of the invention can be used with a VSTB-FET having the cap layer formed from such material as a HT Si3N4, Al2O3, or any dielectric described above. If there is a Si3N4 cap layer, the transistor can have a gate electrode stack fabricated from various materials, including metals and…
How does the proposed scanning electron microscopy (SEM) image enhancement system identify a specific feature within a lower-resolution image by utilizing a higher-resolution reference image?
Labelled document: Systems and methods for SEM image enhancement — US patent application — 2025
30. The system of clause 29, wherein the one or more spatial-spectral characteristics obtained include phase and amplitude characteristics. 31. The system of clause 29, wherein the one or more numerical compensations are applied in a Fourier domain. 32. The system of clause 29, wherein the one or…
In the patent for HDR image tone mapping systems, how does the unified return buffer (URB) facilitate data management and synchronization among threads executing on the graphics core array?
Labelled document: Tone mapping of HDR images for deep learning — US patent application — 2025
Output data generated by threads executing on the graphics core array 414 can output data to memory in a unified return buffer (URB) 418 . The URB 418 can store data for multiple threads. In some embodiments the URB 418 may be used to send data between different threads executing on the graphics…
What problems can occur when the source/drain epitaxial regions of adjacent fins touch or merge in the described semiconductor device with confined epitaxial regions?
Labelled document: Confined epitaxial regions for semiconductor devices — U.S. Patent — 2014
Referring only to part (a) of FIG. 1 , the epitaxial source/ drain regions 110 A of the pair of semiconductor fin structures 102 and 104 are merged (e.g., “fully merged epi”). Such merging of epitaxial material can lead to shorting of adjacent devices. Critical design rules of minimum fin-to-fin…
In the dual path configuration Integrated LiDAR architecture patent, what is the primary benefit of using a system-in-a-package setup that separates the optical switch photonic integrated circuit from its electronic driver circuit?
Labelled document: Integrated LiDAR architecture — US patent — 2019
In the architecture 1400 illustrated in FIG. 14 , the optical beam scanning module is implemented in a system in a package configuration having therefore a driver electronic circuit 1401 of the optical switch being on a separate chip compared to the optical switch photonic integrated circuit (PIC)…
At what point during the gate-last manufacturing process are the sacrificial materials removed to release the nanowires in these stacked transistor channel regions?
Labelled document: Stacked transistor structures with nanowire channels — US patent — 2022
FIGS. 5 a and 5 b each illustrate a cross-sectional view of an integrated circuit structure, in accordance with an embodiment of the present disclosure. The cross-section is taken parallel to the gate and through the channel region. Note that FIGS. 5 a and 5 b show the fin structure after the…
What amounts of decafluorobiphenyl and 1-naphthol are reacted together to synthesize the monomer 8FNE used in the production of fluorinated poly(naphthyl ether)s?
Labelled document: Fluorinated poly(naphthyl ethers) — US Patent — 1992
The monomer 4,4'-bis(1-naphthoxy)octafluorobiphenyl (8FNE) was prepared by the following procedure. A 100 mL round bottom flask was charged with decafluorobiphenyl (3.01 g, 0.0090 mole), 1-naphthol (2.60 g, 0.0181 mole), potassium carbonate (2.95 g, 0.0218 mole), and DMAc (40 g). The mixture was…
In the patent for a high efficiency voltage multiplier circuit, how are the first and fourth capacitors connected to the output terminals of the first and second circuit parts?
Labelled document: US7741898B2 — Patent for high efficiency voltage multiplier circuit and method — 2010
7. The circuit according to claim 1 , wherein the first set of control clock signals includes a first clock signal, a second clock signal, and a third clock signal coupled to the first circuit part respectively by a first capacitor, a second capacitor, and a third capacitor, and the second set of…
How does data travel from an ISP or host computer to a computer system used for semiconductor patterning process model training and pattern ranking?
Labelled document: Methods for training a process model and ranking hot spots — US patent — 2024
Network link 120 typically provides data communication through one or more networks to other data devices. For example, network link 120 may provide a connection through local network 122 to a host computer 124 or to data equipment operated by an Internet Service Provider (ISP) 126 . ISP 126 in…
In this semiconductor device patent disclosure, what three specific types of structures can serve as the first conductive feature?
Labelled document: US10685873B2 — Patent for a semiconductor device with etch stop layer — 2020
In one exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes…
What specific file formats represent the initial design pattern and the resulting OPC-ILT-enhanced mask layout according to this lithographic mask manufacturing patent?
Labelled document: Method for manufacturing lithographic mask for integrated circuit — US Patent — 2018-2021
17 . The method of claim 16 , further comprising training the convolutional neural network based on the database stored in the memory. 18 . The method of claim 14 , wherein the first integrated circuit layout pattern comprises a graphic design system (GDS) file, and wherein the OPC-ILT-enhanced…
In the semiconductor device fabrication method featuring epitaxial layer stacks, how is the dielectric spacer arranged relative to the first and second semiconductor layers in the first source/drain region?
Labelled document: Semiconductor device fabrication method — US patent — 2018
What is claimed is: 1. A device comprising: a first fin and a second fin disposed over a substrate; a first gate structure disposed over the first fin, the first gate structure including: a first gate dielectric layer; and a first semiconductor layer having a top surface facing away from the…
In the gateway apparatus patent disclosure, what security action is taken when an endpoint possesses encrypted DNS features but does not support auto-configuration?
Labelled document: US11711399B2 patent — Gateway apparatus for secure DNS policy enforcement — 2023
There is further disclosed an example of one or more tangible, non-transitory computer-readable storage media, wherein the security policy comprises blocking the outgoing packet if the endpoint has encrypted DNS and auto-configuration capabilities. There is further disclosed an example of one or…
Why is it beneficial to enclose the multiple MEMS transducers within fluidly-isolated, hermetically-sealed cavities in this microelectronic package method?
Labelled document: Microelectronic packages with axially-partitioned hermetic cavities — US patent — 2018
It is thus desirable to provide embodiments of a microelectronic package including at least two MEMS transducer structures, such as accelerometer and gyroscope transducer structures, which are enclosed in fluidly-isolated hermetic cavities. In this manner, a different pressure may be sealed within…
In the patent for semiconductor devices featuring non-volatile memory and high-voltage field-effect transistors, what etching technique is used to strip the NV gate stack dielectric layers from the shallow trench isolation divots?
Labelled document: Semiconductor devices with 2T memory cells — US Patent — 2019-2020
Next, referring to FIG. 4 A , FIGS. 5 F and 5 G , a patterned mask layer 582 is formed on or overlying the sacrificial oxide layer 534 , cap layer 532 and charge- trapping layer 530 , and tunnel dielectric layer 528 disposed outside of the NVM transistor(s) 326 area in the first region 308 and the…
In the semiconductor structure manufacturing method, how is the upper source/drain region shaped after epitaxial growth to prepare its top surface for additional manufacturing steps?
Labelled document: Method for forming a vertical field effect transistor with U-shaped top spacer — US Patent — US10332800B2
In one or more embodiments, a VFET process is defined which advantageously enables the top source/ drain epitaxial region 42 to be formed with a high thermal budget, to minimize defects stemming from epitaxial growth, and to minimize sheet resistance. In one or more embodiments, a VFET replacement…