mi-go · FPGA routing on GPU

The first GPU router in which the parallel routing itself produces legal results, independently verified.

Legal FPGA routes across four public benchmark designs, from a small SoC to a Titan-class miner, each checked by an independent verifier.

799,403
nets, legal
13.7M
node graph
196 s
to legal
96 GB
single GPU

Measured results

Four public FPGA benchmark designs. Every figure below is measured on the routed output.

Design Nets Result Detail
picosoc 4,055 legal in ~0.5 s 2.4x faster than VPR 9
neuron 50,835 legal in ~12 s 1.25x faster than VPR at like-for-like width
sparcT2 Titan class 182,090 legal verified 3 of 3 runs
bitcoin_miner Titan class 799,403 13.7M-node graph legal in 196 s single 96 GB workstation GPU

The honest split

Faster than the reference on small and medium designs, both fully legal; at the largest scales the demonstrated property is verified legality on a single GPU, which no published GPU router has.

Verification

Every routed result is checked two ways: an independent occupancy recount and a full connectivity check. The results are deterministic across repeated runs.

On sparcT2, the router reached a legal result in 3 of 3 runs.

Occupancy
independent recount
Connectivity
full check
Deterministic
across repeated runs

Watch a routing run

Coming

Demo video coming

A recorded routing run will appear here.

Whitepaper

Full method and results

The whitepaper with the complete write-up will be linked here.

Whitepaper (coming)

Patent status

Filed

U.S. Patent Application No. 19/731,882, filed July 2026.

Talk to the team

For technical detail, benchmarking on your own designs, or licensing, get in touch.

Contact Voxell